The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a stacked FinFET fuse and a method of forming such a semiconductor structure.
Monolithic three-dimensional (3D) integration is considered as an alternative approach to ultra-expensive extreme ultra-violet (EUV) techniques to continue density scaling. One scenario is to stack an n-type field effect transistor (i.e., nFET) and a p-type field effect transistor (i.e., pFET) on top of each other creating a stacked FinFET structure.
Stacked FinFET structures need fuses. Fuses are used in a variety of circuit applications. It is highly desired to fabricate on-chip fuses during stacked FinFET complementary metal oxide semiconductor (CMOS) fabrication to minimize cost and improve system integration. Using the same structure and source/drain regions as the high performance FinFET will simplify process complexity. Therefore, there is a need for providing stacked FinFET fuses for use in stacked FinFET structures.